1. Field of the Invention
The present invention relates to a display device, and more particularly, to a test pad of a liquid crystal display (LCD) device.
2. Discussion of the Related Art
CRT Braun tubes have been widely used for monitors of televisions and computers to achieve a relatively easy display of colors and a rapid operation time.
However, CRT Braun tubes tend to have high power consumption. In a typical CRT Braun tube, a certain distance is needed between an electron gun and a screen. This distance makes it difficult to construct compact CRT Brown tubes. Also, a CRT Braun tube is typically heavy, so that it is hard to carry. To solve these problems, various display devices have been studied. Among these display devices, LCD devices have been widely used.
An LCD device can be manufactured to have a relatively thin structure, so that the LCD device can be used as an ultra thin display device for a wall-tapestry television set, for example. Also, LCD devices are light in weight and tend to have low power consumption. For these reasons, LCD devices have attracted attention as substitutes for CRT Braun tubes. For example, LCD devices are now widely used for notebook computers operated by batteries.
As shown in FIG. 1, an LCD device includes a lower substrate 1 having a TFT as a switching device, an upper substrate 2 having a color filter, and a liquid crystal 3 formed between the lower substrate 1 and the upper substrate 2. Even though the LCD device does not emit light itself, picture images are displayed by an electro-optical mechanism of the liquid crystal.
As shown in FIG. 1, TFT array 4 is formed on the lower substrate 1, and a black matrix 5, a color filter film 6, a common electrode 7, and an alignment film 8 are sequentially formed on the upper substrate 2.
The lower substrate 1 and the upper substrate 2 are attached to each other by a sealant 9, which may be, for example, an epoxy resin. Then, a driving circuit 11 and a printed circuit board (PCB) 10 is connected to the lower substrate 1 through a tape carrier package (TCP) 12.
In the TFT array 4, a plurality of gate lines and data lines are formed to cross each other, and a plurality of TFTs are formed at intersections of the gate lines and the data lines.
The LCD device is divided into three parts: an LCD panel, a printed circuit board (PCB), and an external part. The LCD panel includes two substrates having liquid crystal. The PCB injected therebetween has drivers that drive the LCD panel and internal circuitry. The external part includes a backlight.
FIG. 2 is a module diagram showing a structure of the LCD panel and the driver.
As shown in FIG. 2, the LCD device includes an LCD panel 21, a gate driver 23 that drives a gate driving signal to the LCD panel 21, and a source driver 25 that applies signal data to the LCD panel 21.
The gate driver 23 generates scan signals sequentially to a plurality of gate lines arranged on the LCD panel 21. Then, the source driver 25 applies a signal voltage through the data lines when the gate driver 23 turns on the TFTs.
In the LCD panel, the plurality of gate lines and data lines have a matrix structure. A TFT and a pixel electrode are formed at each intersection of the gate lines and data lines. If a TFT is turned on by the scan signal that is applied from the gate driver 23 to the gate lines, the signal voltage applied from the source driver 25 to the data lines is transmitted to the pixel electrodes through the TFTs, thereby displaying a picture image.
At this time, a plurality of gate pads and data pads are extended, respectively, from the gate lines and data lines in the vicinity of the LCD panel 21 to transmit signals generated from the gate driver 23 and the source driver 25 to the LCD panel. The gate pads and data pads are connected to shorting bars to perform testing. When the testing is completed, the shorting bar is removed.
The tests can be classified into an In Processing Test (IPT) and an on/off test of a TFT.
The IPT tests for a line defect or a point defect of the gate and data lines after the lower substrate 1 is formed. The on/off test of a TFT tests for a defect in the on/off operation of a TFT after the lower substrate 1 and the upper substrate 2 are attached to each other.
The structure of a test pad according to a related art LCD device will be described in detail.
FIG. 3 is a plan view showing the structure of the test pad according to the related art LCD device.
As shown in FIG. 3, the test pad includes a first shorting bar 31a, a second shorting bar 31b, a first test pad 33a, a second test pad 33b, a third shorting bar 31c, a fourth shorting bar 31d, a third test pad 33c, and a fourth test pad 33d. 
The first shorting bar 31a is connected to odd numbered data pads (Dp1, Dp3, . . . ) among a plurality of data pads (Dp1 to Dpn) and the second shorting bar 31b is connected to even numbered data pads (Dp2, Dp4 . . . ). Then, the first test pad 33a applies a signal voltage for testing to the first shorting bar 31a, and the second test pad 33b is formed in a different portion of the pad region than the first test pad 33a to apply the signal voltage for testing to the second shorting bar 31b. The third shorting bar 31c is connected to odd numbered gate pads (Gp1, Gp3, . . . ) among a plurality of gate pads (Gp1 to Gpn), and the fourth shorting bar 31d is connected to even numbered gate pads (Gp2, GP4, . . . ). Then, the third test pad 33c applies a signal voltage for testing to the third shorting bar 31c, and the fourth test pad 33d is formed on a different portion of the pad region than the third test pad 33c to apply the signal voltage for testing to the fourth shorting bar 31d. 
Each gate pad is extended from gate lines (G1, G2, . . . , Gm) arranged on the LCD panel 100. Each data pad is extended from data lines (D1, D2, . . . , Dn) arranged on the LCD panel to cross gate lines.
FIG. 4 is an enlarged plan view of the first test pad of FIG. 3. FIG. 5A is a sectional view of the first test pad taken along line I-I′ of FIG. 4.
As shown in FIG. 4 and FIG. 5A, a substrate 100a is formed, and a gate insulating film 101 is formed on the substrate 100a. Then, the first test pad 33a is formed on the gate insulating film 101 and is electrically connected to the first shorting bar 31a. A passivation film 102 is formed on an entire surface of the substrate 100a including the first test pad 33a and includes a contact hole to expose a predetermined portion of the first test pad 33a. Then, a transparent conductive film 37 is electrically connected to the first test pad 33a through the contact hole of the passivation film 102.
FIG. 5B is a sectional view of the third test pad of the gate side taken along line I-I′ of FIG. 3.
As shown in FIG. 5B, the substrate 100a is formed, and the third test pad 33c is formed on the substrate 100a. Then, the gate insulating film 101 is formed on the entire surface of the substrate 100a including the third test pad 33c, and the passivation film 102 is formed on the gate insulating film 101. The transparent conductive film 37 is electrically connected to the third test pad 33c by penetrating the passivation film 102 and the gate insulating film 101.
In the test pad according to the related art LCD device, the first test pad 33a is formed in a predetermined portion of the pad region to apply the signal voltage for testing to the first shorting bar 31a, and the second test pad 33b is formed in a different portion of the pad region than the first test pad 33a to apply the signal voltage for testing to the second shorting bar 31b. Also, the third test pad 33c that applies the signal voltage for testing to the third shorting bar 31c is formed in a different portion of the pad region than the fourth test pad 33d applying the signal voltage to the fourth shorting bar 31d. 
The test pad according to the related art LCD device has the following problems.
In forming the test pads of the gate and data sides, a test pad that applies a signal voltage for testing to the odd numbered data pads or gate pads is formed in a different portion of the pad region than the test pad that applies a signal voltage for testing to the even numbered data pads or gate pads when on/off testing of the TFT is performed. As a result, a resistance value of the shorting bar is high.
With a high resolution of the LCD device, an area of the test pad becomes smaller. In the test pad according to the related art LCD device, because the test pads are formed in the different portions, the resistance of the shorting bar is increased. Therefore, a width of the shorting bar has to be increased to decrease the resistance.